Japanese Patent Application Publication No. 2007-242852 describes a trench-gate-type MOSFET. This MOSFET includes a semiconductor substrate including a trench in an upper surface of the semiconductor substrate, an upper electrode provided on the upper surface of the semiconductor substrate, a lower electrode provided on a lower surface of the semiconductor substrate, and a gate electrode provided within the trench via a gate insulating film. The semiconductor substrate includes a p-type body layer being in contact with the upper electrode, an n-type drift layer intervening between the body layer and the lower electrode, a p-type floating region located within the drift layer and provided along a bottom surface of the trench, and a p-type connection region extending between the body layer and the floating region along a side surface of the trench.
In the MOSFET described above, the floating region is provided along the bottom surface of the trench and the connection region connecting the floating region to the body region is provided along the side surface of the trench. Such a configuration alleviates electric field strength near the bottom surface of the trench when the MOSFET is turned off, and thus the MOSFET withstands a higher voltage. Further, when the MOSFET is turned on, holes are quickly introduced into the floating region from the body layer through the connection region, and thus a charge-up phenomenon in the floating region is suppressed.